Vitis-Tutorials 実行中のエラー

[u_pachiras]

お世話になります。

Vitis-Tutorial を実行中にエラーが発生いたしました。

具体的な場所としましては、以下のページ

/tools/repo/Xilinx/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/dataflow_viewer.md

Viewing the Dataflow Graph after RTL co-simulation
のセクションになります。

Co-simulation を開始するために OK を実行すると、以下のエラーが発生します。

Starting C/RTL cosimulation …
/tools/Xilinx/Vitis_HLS/2020.2/bin/vitis_hls /home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj/solution1/cosim.tcl
INFO: Applying HLS Y2K22 patch v1.2 for IP revision
INFO: [HLS 200-10] Running ‘/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls’
INFO: [HLS 200-10] For user ‘u_pachiras’ on host ‘as101’ (Linux_x86_64 version 3.10.0-1127.19.1.el7.x86_64) on Sun Apr 23 14:24:19 JST 2023
INFO: [HLS 200-10] On os Ubuntu 18.04.6 LTS
INFO: [HLS 200-10] In directory ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow’
Sourcing Tcl script ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj/solution1/cosim.tcl’
INFO: [HLS 200-1510] Running: open_project proj
INFO: [HLS 200-10] Opening project ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj’.
INFO: [HLS 200-1510] Running: set_top diamond
INFO: [HLS 200-1510] Running: add_files diamond.cpp
INFO: [HLS 200-10] Adding design file ‘diamond.cpp’ to the project
INFO: [HLS 200-1510] Running: add_files -tb result.golden.dat -cflags -Wno-unknown-pragmas -csimflags -Wno-unknown-pragmas
INFO: [HLS 200-10] Adding test bench file ‘result.golden.dat’ to the project
INFO: [HLS 200-1510] Running: add_files -tb diamond_test.cpp -cflags -Wno-unknown-pragmas -csimflags -Wno-unknown-pragmas
INFO: [HLS 200-10] Adding test bench file ‘diamond_test.cpp’ to the project
INFO: [HLS 200-1510] Running: open_solution solution1 -flow_target vivado
INFO: [HLS 200-10] Opening solution ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj/solution1’.
INFO: [SYN 201-201] Setting up clock ‘default’ with a period of 5ns.
INFO: [HLS 200-10] Setting target device to ‘xcvu9p-flga2104-2-i’
INFO: [HLS 200-1505] Using flow_target ‘vivado’
Resolution: For help on HLS 200-1505 see http://www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-1510] Running: create_clock -period 5 -name default
INFO: [HLS 200-1510] Running: cosim_design -enable_dataflow_profiling
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench …
Build using “/tools/Xilinx/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++”
Compiling diamond.cpp_pre.cpp.tb.cpp
Compiling apatb_diamond.cpp
Compiling diamond_test.cpp_pre.cpp.tb.cpp
Compiling apatb_diamond_ir.ll
Generating cosim.tv.exe
Makefile.rules:392: recipe for target ‘cosim.tv.exe’ failed
e-m:e-i64:64-i128:128-i256:256-i512:512-i1024:1024-i2048:2048-i4096:4096-n8:16:32:64-S128-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024/tools/Xilinx/Vivado/2020.2/tps/lnx64/binutils-2.26/bin/ld: crt1.o が見つかりません: そのようなファイルやディレクトリはありません
/tools/Xilinx/Vivado/2020.2/tps/lnx64/binutils-2.26/bin/ld: crti.o が見つかりません: そのようなファイルやディレクトリはありません
/tools/Xilinx/Vivado/2020.2/tps/lnx64/binutils-2.26/bin/ld: -lpthread が見つかりません
/tools/Xilinx/Vivado/2020.2/tps/lnx64/binutils-2.26/bin/ld: -lm が見つかりません
collect2: エラー: ld はステータス 1 で終了しました
make: *** [cosim.tv.exe] Error 1
ERROR: [COSIM 212-317] C++ compile error.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-331] Aborting co-simulation: C simulation failed, compilation errors.
ERROR: [COSIM 212-5] *** C/RTL co-simulation file generation failed. ***
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***

———————————

crt1.o, crti.o といったファイルがないようです。
ネットを検索してみると、glibc の開発版パッケージが足りない等の情報が出てくるのですが、
何か分かりますでしょうか？

環境は as101 上で以下の設定を実施しております。
source /tools/Xilinx/Vitis/2022.2/settings64.sh
source /opt/xilinx/xrt/setup.sh

よろしくお願いいたします。

[u_pachiras]

失礼しました。上記のログは Vitis 2020.2 の結果でした。
しかしながら、Vitis 2022.2 で実施した場合でも以下のように同じエラーが発生しました。

Starting C/RTL cosimulation …
/tools/Xilinx/Vitis_HLS/2022.2/bin/vitis_hls /home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj/solution1/cosim.tcl
INFO: [HLS 200-10] Running ‘/tools/Xilinx/Vitis_HLS/2022.2/bin/unwrapped/lnx64.o/vitis_hls’
INFO: [HLS 200-10] For user ‘u_pachiras’ on host ‘as101’ (Linux_x86_64 version 3.10.0-1127.19.1.el7.x86_64) on Sun Apr 23 20:47:00 JST 2023
INFO: [HLS 200-10] On os Ubuntu 18.04.6 LTS
INFO: [HLS 200-10] In directory ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow’
Sourcing Tcl script ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj/solution1/cosim.tcl’
INFO: [HLS 200-1510] Running: source /home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj/solution1/cosim.tcl
INFO: [HLS 200-1510] Running: open_project proj
INFO: [HLS 200-10] Opening project ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj’.
INFO: [HLS 200-1510] Running: set_top diamond
INFO: [HLS 200-1510] Running: add_files diamond.cpp
INFO: [HLS 200-10] Adding design file ‘diamond.cpp’ to the project
INFO: [HLS 200-1510] Running: add_files -tb result.golden.dat -cflags -Wno-unknown-pragmas -csimflags -Wno-unknown-pragmas
INFO: [HLS 200-10] Adding test bench file ‘result.golden.dat’ to the project
INFO: [HLS 200-1510] Running: add_files -tb diamond_test.cpp -cflags -Wno-unknown-pragmas -csimflags -Wno-unknown-pragmas
INFO: [HLS 200-10] Adding test bench file ‘diamond_test.cpp’ to the project
INFO: [HLS 200-1510] Running: open_solution solution1 -flow_target vivado
INFO: [HLS 200-10] Opening solution ‘/home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/proj/solution1’.
INFO: [SYN 201-201] Setting up clock ‘default’ with a period of 5ns.
INFO: [HLS 200-1611] Setting target device to ‘xcvu9p-flga2104-2-i’
INFO: [HLS 200-1505] Using flow_target ‘vivado’
Resolution: For help on HLS 200-1505 see http://www.xilinx.com/cgi-bin/docs/rdoc?v=2022.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1464] Running solution command: config_interface -m_axi_latency=0
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-1510] Running: create_clock -period 5 -name default
INFO: [HLS 200-1510] Running: config_interface -m_axi_latency 0
INFO: [HLS 200-1510] Running: cosim_design -enable_dataflow_profiling
Running Dispatch Server on port: 43779
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench …
Build using “/tools/Xilinx/Vitis_HLS/2022.2/tps/lnx64/gcc-8.3.0/bin/g++”
Compiling diamond.cpp_pre.cpp.tb.cpp
Compiling apatb_diamond.cpp
Compiling diamond_test.cpp_pre.cpp.tb.cpp
Compiling apatb_diamond_ir.ll
Generating cosim.tv.exe
Makefile.rules:322: recipe for target ‘cosim.tv.exe’ failed
e-m:e-i64:64-i128:128-i256:256-i512:512-i1024:1024-i2048:2048-i4096:4096-n8:16:32:64-S128-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024/tools/Xilinx/Vivado/2022.2/tps/lnx64/binutils-2.37/bin/ld: cannot find crt1.o: No such file or directory
/tools/Xilinx/Vivado/2022.2/tps/lnx64/binutils-2.37/bin/ld: cannot find crti.o: No such file or directory
/tools/Xilinx/Vivado/2022.2/tps/lnx64/binutils-2.37/bin/ld: cannot find -lpthread
/tools/Xilinx/Vivado/2022.2/tps/lnx64/binutils-2.37/bin/ld: cannot find -lm
collect2: error: ld returned 1 exit status
make: *** [cosim.tv.exe] Error 1
ERROR: [COSIM 212-317] C++ compile error.
ERROR: [COSIM 212-321] EXE file generate failed.
ERROR: [COSIM 212-331] Aborting co-simulation: C simulation failed, compilation errors.
ERROR: [COSIM 212-5] *** C/RTL co-simulation file generation failed. ***
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 1.97 seconds. CPU system time: 0.68 seconds. Elapsed time: 3.85 seconds; current allocated memory: 0.000 MB.
command ‘ap_source’ returned error code
while executing
“source /home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/dataflow/…”
invoked from within
“hls::main /home/u_pachiras/workspace/Vitis-Tutorials/Hardware_Acceleration/Feature_Tutorials/03-dataflow_debug_and_optimization/reference_files/datafl…”
(“uplevel” body line 1)
invoked from within
“uplevel 1 hls::main {*}$newargs”
(procedure “hls_proc” line 16)
invoked from within
“hls_proc [info nameofexecutable] $argv”
INFO: [HLS 200-112] Total CPU user time: 3.79 seconds. Total CPU system time: 0.94 seconds. Total elapsed time: 16.1 seconds; peak allocated memory: 848.633 MB.
Finished C/RTL cosimulation.

[ando]

以下のようにLIBRARY_PATHを設定することで解消するようですのでお試しください。

export LIBRARY_PATH=/usr/lib/x86_64-linux-gnu:$LIBRARY_PATH

https://support.xilinx.com/s/question/0D52E00006hpJpSSAU/vivado-hls-c-simulation-and-crtl-cosimulation-running-debiantesting?language=ja

[u_pachiras]

ando 様、

返信が遅れまして申し訳ありません。お知らせいただいたように環境変数を設定したところ、
うまく動きました！お忙しいところありがとうございました。

[投稿者]

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